[1]赵文虎,王志功,吴微,等.千兆以太网同步检测集成电路设计[J].东南大学学报(自然科学版),2002,32(2):161-165.[doi:10.3969/j.issn.1001-0505.2002.02.003]
 Zhao Wenhu,Wang Zhigong,Wu Wei,et al.Gigabit-Ethernet synchronization detector integrated circuit[J].Journal of Southeast University (Natural Science Edition),2002,32(2):161-165.[doi:10.3969/j.issn.1001-0505.2002.02.003]
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千兆以太网同步检测集成电路设计()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
32
期数:
2002年第2期
页码:
161-165
栏目:
电子科学与工程
出版日期:
2002-03-20

文章信息/Info

Title:
Gigabit-Ethernet synchronization detector integrated circuit
作者:
赵文虎 王志功 吴微 李本靖
东南大学射频与光电集成电路研究所,南京 210096
Author(s):
Zhao Wenhu Wang Zhigong Wu Wei Li Benjing
Institute of RF-&OE-Ics, Southeast University, Nanjing 210096, China
关键词:
千兆以太网 码组检测 互连线
Keywords:
gigabit-Ethernet comma-detector interconnection
分类号:
TN722.7
DOI:
10.3969/j.issn.1001-0505.2002.02.003
摘要:
采用两级分接电路结构,并将同步码字检测电路置于其间,设计了千兆以太网同步检测集成电路.实现1.25 Gb/s速率的千兆以太网数据由1路到10路的串并转换以及同步码字的检测.分析了RC网络效应对超高速集成电路中互连线的影响,基于TSMC 0.35 μm CMOS工艺建立电路模型.使用Smartspice工具在不同温度(0~70 ℃)、电源电压(3.15~3.45 V)及输入信号等条件下进行仿真.结合版图参数提取后仿真的比较,证明了该设计在减小规模,简化结构和加快仿真流程方面的有效性.电路版图采用全定制方式实现.
Abstract:
This paper presents a structure of comma-detector in cascade DEMUX to the achievement of 1.25 Gb/s operations including 1:10 demultiplexer, comma detection and word alignment logic. Considering the serious RC network effects of interconnections in very high speed digital ICs, the parasitic parameters of the interconnections with TSMC 0.35 μm CMOS process were extracted and added into the netlist. The re-simulations were compared at different temperature(0-70 ℃), various power supply voltages(3.15-3.45 V)and various input signal with Smartspice. The layout was finished in full custom. This structure can improve the design efficiency and reduce the circuit scale.

参考文献/References:

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[5] Fukaishi M,Nakamura K,Heiuchi H,et al.A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays [J].IEEE Journal of Solid-State Circuits,2000,35(11):1611-1618.
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相似文献/References:

[1]郁炜嘉,朱恩,程树东,等.0.18-μm CMOS千兆以太网并串转换芯片设计[J].东南大学学报(自然科学版),2004,34(3):293.[doi:10.3969/j.issn.1001-0505.2004.03.002]
 Yu Weijia,Zhu En,Cheng Shudong,et al.0.18-μm CMOS serializer for gigabit Ethernet[J].Journal of Southeast University (Natural Science Edition),2004,34(2):293.[doi:10.3969/j.issn.1001-0505.2004.03.002]

备注/Memo

备注/Memo:
基金项目: 国家自然科学基金资助项目(69825101).
作者简介: 赵文虎(1974—), 男, 博士生, zhaowh@seu.edu.cn; 王志功(联系人), 男, 博士, 教授, 博士生导师,zgwang@seu.edu.cn.
更新日期/Last Update: 2002-03-20