[1]乔庐峰,王志功,经继松,等.多光口SDH网元中DCC通道速率适配电路的设计与实现[J].东南大学学报(自然科学版),2003,33(6):703-706.[doi:10.3969/j.issn.1001-0505.2003.06.006]
 Qiao Lufeng,Wang Zhigong,Jing Jisong,et al.Design of DCC multiplexer used in complex SDH network elements[J].Journal of Southeast University (Natural Science Edition),2003,33(6):703-706.[doi:10.3969/j.issn.1001-0505.2003.06.006]
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多光口SDH网元中DCC通道速率适配电路的设计与实现()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
33
期数:
2003年第6期
页码:
703-706
栏目:
电子科学与工程
出版日期:
2003-11-20

文章信息/Info

Title:
Design of DCC multiplexer used in complex SDH network elements
作者:
乔庐峰12 王志功1 经继松2 黄颋1 王晓明1
1 东南大学射频与光电集成电路研究所, 南京 210096; 2 解放军理工大学通信工程学院, 南京 210007
Author(s):
Qiao Lufeng12 Wang Zhigong1 Jing Jisong2 Huang Ting1 Wang Xiaoming1
1 Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
2 Institute of Communication Engineering, PLA University of Science and Technology, Nanjing 210007, China
关键词:
现场可编程门阵列 同步数字序列 高级数据链路控制 数据通信通道 网络管理
Keywords:
field programmable logic array(FPGA) synchronous digital hierarchy(SDH) high level data link control(HDLC) data communication channel(DCC) network management
分类号:
TN722
DOI:
10.3969/j.issn.1001-0505.2003.06.006
摘要:
采用现场可编程门阵列(FPGA),设计了一种用于SDH传输系统中数据通信通道(DCC)数据帧汇聚与速率适配的电路.可以将具有不同时钟的12个独立DCC通道中的HDLC数据帧进行提取、缓存并复接成一个时分复用的高速数据链路,交给Motorola MPC860中的多通道通信控制器进行处理.整个设计采用一片XILINX 的xc2s200pq208完成,使用约17万等效门,在HDLC最大帧长为1 kB的情况下,允许的多通道通信控制器与DCC 通道时钟之间的时钟偏差大于1.4%,并给出了测试波形.
Abstract:
This paper presents a new method used in SDH transmission systems to converge the HDLC data frames from 12 independent data communication channels(DCC)into one time-division multiplexing data link. HDLC packets from DCC channels with different clocks can be abstracted, buffered, and inserted into different timeslots of a high speed data link and sent to the multi-channel HDLC controller embedded in the Motorola MPC860 processor. The design is implemented with an XILINX xc2s200pq208 and approximately 170 000 equivalent gates are possessed. With HDLC packet length less than 1 kbytes, the tolerance of clock difference between the multi-channel HDLC controller and DCC channels can exceed 1.4%. The tested waveform is presented.

参考文献/References:

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[3] Motorola Inc.MPC860 User Manual[EB/OL].http://e-www.motorola.com/brdata/PDFDB/docs/MPC860UM.pdf.2003-04-01/2003-05-06.
[4] Lu Yuanlin,Wang Zhigong,Qiao Lufeng,et al.Design and implementation of multi-channel high speed HDLC data processor [A].In:2002 International Conference on Communications Circuits and Systems and West Sino Expositions Proceedings[C].Chengdu,China:UESTC Press,2002.1471-1475.
[5] Varada S,Oduol V,Shelat A.Data flow and buffer management in multi-channel data link controller[A].In:24th Conference on Local Computer Networks[C].Lowell,Massachusetts,1999.132-141.
[6] Claretto Serafino,Filippi Enrica,Montanaro Achille,et al.Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library[A].In:1997 VHDL International User’s Forum(VIUF ’97)[C].Arlington,VA,1997.88-94.
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备注/Memo

备注/Memo:
作者简介: 乔庐峰(1971—),男,博士生,讲师,qlf@seu.edu.cn; 王志功(联系人),男,博士,教授,博士生导师,zgwang@seu.edu.cn.
更新日期/Last Update: 2003-11-20