[1]杨守军,王志功,朱恩,等.24 Gbit/s 0.2 μm PHEMT复接器[J].东南大学学报(自然科学版),2004,34(3):289-292.[doi:10.3969/j.issn.1001-0505.2004.03.001]
 Yang Shoujun,Wang Zhigong,Zhu En,et al.24 Gbit/s multiplexer using 0.2 μm PHEMT technology[J].Journal of Southeast University (Natural Science Edition),2004,34(3):289-292.[doi:10.3969/j.issn.1001-0505.2004.03.001]
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24 Gbit/s 0.2 μm PHEMT复接器()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
34
期数:
2004年第3期
页码:
289-292
栏目:
电路与系统
出版日期:
2004-05-20

文章信息/Info

Title:
24 Gbit/s multiplexer using 0.2 μm PHEMT technology
作者:
杨守军 王志功 朱恩 冯军 熊明珍 夏春晓
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Yang Shoujun Wang Zhigong Zhu En Feng Jun Xiong Mingzhen Xia Chunxiao
Institute of RF & OE-ICs, Southeast University, Nanjing 210096, China
关键词:
光通信 复接器 SCFL 倍频器
Keywords:
optical communication multiplexer SCFL frequency doubler
分类号:
TN492
DOI:
10.3969/j.issn.1001-0505.2004.03.001
摘要:
本文利用Philips公司OMMIC 0.2 μm GaAs PHEMT工艺,设计出24 Gbit/s的复接器.应用源极耦合FET逻辑(SCFL),使逻辑电路能够在24 Gbit/s速率上正常工作.时钟采用二倍频方案,解决了多级复接中的高速时钟问题.改进异或门拓扑结构实现的二倍频器,结构简单、实用,降低了电路复杂度.利用源极耦合电容的微分作用,加速晶体管开、关转换,提高了选择器工作速度.芯片通过功能测试验证,数据速率可达到24 Gbit/s.
Abstract:
A 24 Gbit/s multiplexer is realized by using OMMIC 0.2 μm PHEMT GaAs technology of Philips. This circuit is designed with SCFL structure. The clock signal is obtained by using a frequency doubler which uses a modified XOR topology, so that the complexity of the system is reduced. The speed of the selector is accelerated by applying a source-coupled capacitor which speeds up the PHEMT switches. The test results of the function verify that this chip can correctly work at 24 Gbit/s.

参考文献/References:

[1] Sano K,Murata K,Sugitani S,et al.50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs [J]. IEEE Journal of Solid-State Circuits,2003,38(9):1504-1511.
[2] Hackl S,Bock J.42 GHz active frequency doubler in SiGe bipolar technology [A].In:IEEE International Conference on Microwave and Millimeter Wave Technology [C].Beijing,2002.54-57.
[3] Lu Jianhua,Tian Lei,Chen Haitao,et al.Design techniques of CMOS SCL circuits for Gb/s application[A].In:ASICON[C].Nanjing,2001.
[4] Suzuki T,Nakasha Y,Sakoda T,et al.A 100-Gbit/s 2:1 multiplexer in InP HEMT technology [A].In:Proceedings of IEEE MTT-S IMS[C].2003.1173-1176.
[5] Wang Zhigong,Berroth M,Nowotny V,et al.7.5 Gbit/s monolithically integrated clock recovery using PLL and 0.3 μm gate length quantum well HEMTs [A].In:Proc of 19th European Solid-State Circuits Conference [C].Sevilla,Spain,1993.222-225.

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 Zhou He,Feng Jun,Guan Xin,et al.Design, package and test of ultra high-speed low power 4〓:1multiplexer[J].Journal of Southeast University (Natural Science Edition),2009,39(3):234.[doi:10.3969/j.issn.1001-0505.2009.02.010]

备注/Memo

备注/Memo:
基金项目: 国家高技术研究发展计划(863计划)资助项目(2001AA312060).
作者简介: 杨守军(1975—),男,博士生; 王志功(联系人),男, 博士, 教授, 博士生导师,zgwang@seu.edu.cn.
更新日期/Last Update: 2004-05-20