[1]郁炜嘉,朱恩,程树东,等.0.18-μm CMOS千兆以太网并串转换芯片设计[J].东南大学学报(自然科学版),2004,34(3):293-296.[doi:10.3969/j.issn.1001-0505.2004.03.002]
 Yu Weijia,Zhu En,Cheng Shudong,et al.0.18-μm CMOS serializer for gigabit Ethernet[J].Journal of Southeast University (Natural Science Edition),2004,34(3):293-296.[doi:10.3969/j.issn.1001-0505.2004.03.002]
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0.18-μm CMOS千兆以太网并串转换芯片设计()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
34
期数:
2004年第3期
页码:
293-296
栏目:
电路与系统
出版日期:
2004-05-20

文章信息/Info

Title:
0.18-μm CMOS serializer for gigabit Ethernet
作者:
郁炜嘉 朱恩 程树东 孙玲 费瑞霞 沈桢 孟凡生 吴春红 王雪艳 王志功
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Yu Weijia Zhu En Cheng Shudong Sun Ling Fei Ruixia Shen ZhenMeng Fansheng Wu Chunhong Wang Xueyan Wang Zhigong
Institute of RF & OE-ICs, Southeast University, Nanjing 210096, China
关键词:
千兆以太网 并串转换 CMOS
Keywords:
gigabit Ethernet serializer CMOS
分类号:
TN432
DOI:
10.3969/j.issn.1001-0505.2004.03.002
摘要:
提出了一种新的树型结构10:1并串转换电路,可应用于千兆以太网,其工作速度达到1.25 Gbit/s.树型结构的使用可以使大部分电路工作在较低的速率上,从而简化了设计,也减小了功耗.低速5:1并串转换单元采用改进的并行结构,利用一系列D触发器调整进入数据选择器的时钟和数据间的相位关系,使其相对于普通并行结构有更大的相位裕量,可以更可靠地工作.芯片应用TSMC 0.18-μm CMOS工艺实现,芯片面积为0.7 mm×0.5 mm,核心电路功耗为3.6 mW,小于同类电路.
Abstract:
A novel tree-type 10:1 serializer is provided. The speed of the serializer, which is used in gigabit Ethernet, is up to 1.25 Gbit/s. Tree-type structure decreases the speed of most modules, which makes design easier, and decreases the power consumption. The parallel-structure used in low-speed 5:1 serialize module is improved, which has bigger phase margin than common ones. The chip was fabricated in TSMC 0.18-μm CMOS process. The chip area is 0.7 mm×0.5 mm, and the power consumption of the core is 3.6 mW, which is smaller than the same kind of circuits.

参考文献/References:

[1] 王志功.光纤通信集成电路设计[M].北京:高等教育出版社,2003.254-258.
[2] Rabaey J M.Digital integrated circuits:a design perspective [M].Englewood Cliffs:Prentice-Hall Inc,1998.511-516.
[3] Yuan J,Svensson C.High-speed CMOS circuit technique [J].IEEE J Solid State Circuits,1989,24(1):62-70.
[4] Afghahi M,Sevensson C.A unified single-phase clocking scheme for VLSI systems [J].IEEE J Solid State Circuits,1990,25(1):225-233.
[5] Wang J S,Yang P H.A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications [A].In: Proc IEEE ISCAS ’98 [C].1998.93-96.

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[1]赵文虎,王志功,吴微,等.千兆以太网同步检测集成电路设计[J].东南大学学报(自然科学版),2002,32(2):161.[doi:10.3969/j.issn.1001-0505.2002.02.003]
 Zhao Wenhu,Wang Zhigong,Wu Wei,et al.Gigabit-Ethernet synchronization detector integrated circuit[J].Journal of Southeast University (Natural Science Edition),2002,32(3):161.[doi:10.3969/j.issn.1001-0505.2002.02.003]

备注/Memo

备注/Memo:
基金项目: 国家高技术研究发展计划(863计划)资助项目(2001AA121074).
作者简介: 郁炜嘉(1979—),男,硕士生; 朱恩(联系人),男,博士,教授,zhuenpro@seu.edu.cn.
更新日期/Last Update: 2004-05-20