[1]沈桢,朱恩,赵文虎,等.10 Gbit/s 0.18 μm CMOS 1:4分接集成电路[J].东南大学学报(自然科学版),2004,34(4):426-429.[doi:10.3969/j.issn.1001-0505.2004.04.002]
 Shen Zhen,Zhu En,Zhao Wenhu,et al.IC design of 10 Gbit/s 0.18 μm CMOS 1:4 DEMUX[J].Journal of Southeast University (Natural Science Edition),2004,34(4):426-429.[doi:10.3969/j.issn.1001-0505.2004.04.002]
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10 Gbit/s 0.18 μm CMOS 1:4分接集成电路()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
34
期数:
2004年第4期
页码:
426-429
栏目:
电路与系统
出版日期:
2004-07-20

文章信息/Info

Title:
IC design of 10 Gbit/s 0.18 μm CMOS 1:4 DEMUX
作者:
沈桢 朱恩 赵文虎 王志功
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Shen Zhen Zhu En Zhao Wenhu Wang Zhigong
Institute of RF & OE-ICs, Southeast University, Nanjing 210096, China
关键词:
万兆以太网 高速分接芯片 CMOS工艺
Keywords:
10 Gigabit Ethernet high-speed demuxplexer integrated circuit CMOS process
分类号:
TN492
DOI:
10.3969/j.issn.1001-0505.2004.04.002
摘要:
研究了万兆以太网接收芯片结构,并在此基础上设计、流片和测试了高速1:4分接芯片,采用0.18 μm CMOS工艺设计的1:4分接电路,实现了满足10GBASE-R的10.312 5 Gbit/s数据的1:4串/并转换,芯片面积1 100 μm×800 μm,在输入单端摆幅为800 mV,输出负载50 Ω条件下,输出2.578 Gbit/s数据信号电压峰峰值为228 mV,抖动为 4 ps RMS, 眼图的占空比为55.9%,上升沿时间为58 ps.在电源为 1.8 V时, 功耗为 500 mW.电路最高可实现13.5 Gbit/s的4路分接.
Abstract:
Based on the research of 10 Gigabit Ethernet demultiplexer structure, a high-speed 1:4 demuxplexer(DEMUX)was designed, fabricated and tested. The DEMUX chips produced in 0. 18 μm CMOS process have a function of 1:4 demultiplexing and can operate at 10. 312 5 Gbit/s satisfying 10GBASE-R. Its area is 1 100 μm×800 μm. Under the condition of 800 mV input swing and 50 Ω output load,the peak-to-peak voltage of 2. 578 Gbit/s output signal is 228 mV, the rising time is 58 ps, and the root mean square(RMS)jitter is 4 ps. The power consumption is 500 mW under 1. 8 V supply voltage. The highest operating data rate tested is 13. 5 Gbit/s.

参考文献/References:

[1] 赵文虎, 王志功,吴微,等.千兆以太网同步检测集成电路设计 [J].东南大学学报(自然科学版),2002,32(2):161-165.
  Zhao Wenhu,Wang Zhigong,Wu Wei,et al.Gigabit-Ethernet synchronization detector integrated circuit [J].Journal of Southeast University(National Science Edition), 2002,32(2):161-165.(in Chinese)
[2] Zhao Wenhu, Wang Zhigong,Shen Zhen,et al.A 3.125 Gb/s CMOS transmitter for serial data communications [A].In:2003 5th International Conference on Proceedings[C].Shanghai,China,2003.1033-1036.
[3] Mattia J P, Pullela R,Baeyens Y,et al.A 1:4 demultiplexer for 40 Gb/s fiber-optic applications [A].In: ISSCC 2000 IEEE International [C].San Francisco,UAS,2000.64-65.
[4] Fukaishi M, Nakamura K,Heiuchi H,et al.A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays[J].IEEE Journal of Solid-State Circuits, 2000,35(11):1611-1618.
[5] Tanabe A, Umetani M,Fujiwara I,et al.0.18-μm CMOS 10Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation[J].IEEE Journal of Solid-State Circuits,2001,36(6):988-996.

备注/Memo

备注/Memo:
基金项目: 国家高技术研究发展计划(863计划)资助项目(2001AA121074).
作者简介: 沈桢(1979—),男,硕士生; 朱恩(联系人),男,博士,教授,博士生导师,zhuenpro@seu.edu.cn.
更新日期/Last Update: 2004-07-20