[1]荣瑜,朱恩.一种高性能FFT蝶形运算单元的设计[J].东南大学学报(自然科学版),2007,37(4):565-568.[doi:10.3969/j.issn.1001-0505.2007.04.004]
 Rong Yu,Zhu En.Design of high-performance FFT butterfly unit[J].Journal of Southeast University (Natural Science Edition),2007,37(4):565-568.[doi:10.3969/j.issn.1001-0505.2007.04.004]
点击复制

一种高性能FFT蝶形运算单元的设计()
分享到:

《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
37
期数:
2007年第4期
页码:
565-568
栏目:
电路与系统
出版日期:
2007-07-20

文章信息/Info

Title:
Design of high-performance FFT butterfly unit
作者:
荣瑜 朱恩
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Rong Yu Zhu En
Institute of RF and OE-ICs, Southeast University, Nanjing 210096, China
关键词:
快速傅立叶变换 蝶形 高性能 流水线 并行 专用集成电路
Keywords:
fast Fourier transform butterfly high-performance pipelined parallel application specific integrted circuit
分类号:
TN46
DOI:
10.3969/j.issn.1001-0505.2007.04.004
摘要:
基于TSMC 0.18 μm CMOS工艺标准单元库,设计了一种高性能快速傅立叶变换蝶形运算单元.蝶形运算是快速傅立叶变换的核心,单元采用时间抽取的快速傅立叶变换基2算法、并行全流水结构,对IEEE 754单精度浮点数构成的复数进行处理,并可在同一个快速傅立叶变换处理器中并行扩展使用.逻辑综合与版图综合后的报告显示单元的核面积为1.96 mm2.仿真结果表明,单元能够稳定运行在200 MHz时钟下,输出数据误差小,使用一个该单元的快速傅立叶变换处理器完成1 024点数据运算需时27.6 μs,其速度、精度及面积完全达到了设计指标.
Abstract:
A high performance FFT(fast Fourier transform)butterfly unit with TSMC(Taiwan semiconductor manufacturing company)0.18 μm CMOS extended cells is designed. As the key part of the FFT processor, the butterfly unit which is based on the FFT algorithm of Radix 2 and DIT(decimation in time)uses parallel pipelined architecture to operate complex number of IEEE 754 Std. single precision format, and it can be parallelly used in one FFT processor. The report of logic and layout synthesis shows that the core area of the unit is 1.96 mm2. The simulation results demonstrate that the unit operates stably at 200 MHz with little output data error; the processor which contains only one of this unit can perform 1 024 FFT every 27.6 μs; and the performances of speed, precision and area totally meet the design requirements.

参考文献/References:

[1] 胡广书.数字信号处理[M].北京:清华大学出版社,2005.
[2] 王志功,朱恩.VLSI设计[M].北京:电子工业出版社,2005.
[3] Wang A,Chandrakasan A.A 180 mV subthreshold FFT processor using a minimum energy design methodology[J].IEEE Journal of Solid-State Circuits,2005,40(3):310-319.
[4] Baas B M.A low-power,high-performance,1024-point FFT processor[J]. IEEE Journal of Solid-State Circuits,1999,34(3):380-387.
[5] 周海斌,刘刚.基于FPGA的高速实时FFT处理器设计[J].电子工程师,2005,31(1):54-56.
  Zhou Haibin,Liu Gang.Design of a high speed and real-time FFT processor with FPGA[J]. Electronic Engineer,2005,31(1):54-56.(in Chinese)
[6] Ciletti M D.Advanced digital design with Verilog HDL[M].Beijing:Publishing House of Electronics Industry,2005.
[7] 刘国栋,陈伯孝,陈多芳.FFT处理器的FPGA设计[J].航空计算技术,2004,34(3):101-104.
  Liu Guodong,Chen Baixiao,Chen Duofang.Design of FFT processor based on FPGA[J].Aeronautical Computer Technique,2004,34(3):101-104.(in Chinese)
[8] Kuo J C,Wen C H,Wu A Y.Implementation of a programmable 64-2048-point FFT/IFFT processor for OFDM-based communication systems[C] //Proceedings of the IEEE International Symposium on Circuits and Systems.Bangkok,Thailand,2003,2:121-124.
[9] Altera Corporation.Floating point FFT processor(IEEE 754 single precision)Radix 2 Core White Paper[EB/OL].(2004-03-12)[2006-05-23].http://www.ieechina.com/Upload/Tech/200403121540180656.pdf.

备注/Memo

备注/Memo:
作者简介: 荣瑜(1982—),男,硕士生; 朱恩(联系人),男,教授,博士生导师, zhuenpro@seu.edu.cn.
更新日期/Last Update: 2007-07-20