[1]周鹤,冯军,管忻,等.超高速低功耗4:1复接器设计、封装及测试[J].东南大学学报(自然科学版),2009,39(2):234-237.[doi:10.3969/j.issn.1001-0505.2009.02.010]
　Zhou He,Feng Jun,Guan Xin,et al.Design, package and test of ultra high-speed low power 4〓:1multiplexer[J].Journal of Southeast University (Natural Science Edition),2009,39(2):234-237.[doi:10.3969/j.issn.1001-0505.2009.02.010]
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超高速低功耗4:1复接器设计、封装及测试()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
39
期数:
2009年第2期
页码:
234-237
栏目:
电子科学与工程
出版日期:
2009-03-20

文章信息/Info

Title:
Design, package and test of ultra high-speed low power 4〓:1multiplexer
作者:
周鹤1;  冯军1;  管忻1;  章丽1;  李伟1;  管志强2
1 东南大学射频与光电集成电路研究所,南京 210096; 2 新志光电集成有限责任公司,南京 210000
Author(s):
Zhou He1;  Feng Jun1;  Guan Xin1;  Zhang Li1;  Li Wei1;  Guan Zhiqiang2
1 Institute of RF and OE ICs, Southeast University, Nanjing 210096, China
2 Sino-Chip OEIC Jiangsu Co. Ltd, Nanjing 210000, China
关键词:
CMOS;  复接器;  低功耗;  封装;  光纤通信
Keywords:
complementary metal oxide semiconductor(CMOS);  multiplexer;  low power;  package;  optical communication
分类号:
TN722
DOI:
10.3969/j.issn.1001-0505.2009.02.010
摘要:
采用CSM 0.35 μm CMOS 工艺,设计了低功耗2.5～3.125 Gbit/s 4:1复接器.该芯片既可以应用于光纤通信系统SDH STM-16(2.5 Gbit/s)速率级别的光发射机,又可以应用于万兆以太网IEEE 802.3ae 10GBASE-X(3.125 Gbit/s)速率级别的通道接口发送器.系统采用树型结构,核心电路由锁存器、选择器、分频器组成,并采用了CMOS逻辑实现.最高工作速率可达3.5 Gbit/s.芯片供电电压3.3 V,核心功耗为25 mW.该芯片采用SOP-16封装.芯片封装后焊接在高速PCB板上进行测试,封装后芯片最高工作速率为2.3 Gbit/s.
Abstract:
A 2.5 to 3.125 Gbit/s 4:1 multiplexer using CSM(chartered semiconductor manufacturing)0.35 μm complementary metal oxide semiconductor(CMOS)process is described. This multiplexer is not only designed for the application of SDH(synchronous digital hierarchy)STM(synchronous transfer mode)-16 system but also for IEEE 802.3ae 10GBASE-X. The tree-type structure is adopted. The core circuits are composed of latches, selectors and a frequency divider. The core part is totally realized by CMOS logic for it has no static power consumption. Output data rate is up to 3.5 Gbit/s. The core power consumption of the chip is about 25 mW at a supply voltage of 3.3 V. Small out-line package(SOP)-16 is adopted. A high-speed printed circuit board(PCB)which is used in the packaged chip test is designed and produced. Output data rate of the packaged chip is up to 2.3 Gbit/s.

参考文献/References:

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备注/Memo

备注/Memo:
作者简介: 周鹤(1984—),男,硕士生; 冯军(联系人),女,教授,博士生导师,fengjun_seu@seu.edu.cn.
引文格式: 周鹤,冯军,管忻,等.超高速低功耗4:1复接器设计、封装及测试[J].东南大学学报:自然科学版,2009,39(2):234-237.
更新日期/Last Update: 2009-03-20