[1]徐捷,胡庆生,许多,等.40 Gbit/s甚短距离光传输系统发送模块的设计与实现[J].东南大学学报(自然科学版),2009,39(4):656-661.[doi:10.3969/j.issn.1001-0505.2009.04.002]
 Xu Jie,Hu Qingsheng,Xu Duo,et al.Design and implementation of transmitter module in 40 Gbit/s very short reach optical transmission system[J].Journal of Southeast University (Natural Science Edition),2009,39(4):656-661.[doi:10.3969/j.issn.1001-0505.2009.04.002]
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40 Gbit/s甚短距离光传输系统发送模块的设计与实现()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
39
期数:
2009年第4期
页码:
656-661
栏目:
信息与通信工程
出版日期:
2009-07-20

文章信息/Info

Title:
Design and implementation of transmitter module in 40 Gbit/s very short reach optical transmission system
作者:
徐捷 胡庆生 许多 苗澎
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Xu Jie Hu Qingsheng Xu Duo Miao Peng
Institute of RF- and OE-ICs, Southeast University, Nanjing 210096, China
关键词:
甚短距离 高速收发器 16:12转换器 帧同步 去斜移
Keywords:
very short reach high speed transceiver 16:12 converter frame synchronization deskew
分类号:
TN929
DOI:
10.3969/j.issn.1001-0505.2009.04.002
摘要:
采用Altera公司的Stratix Ⅱ GX FPGA,实现40 Gbit/s甚短距离光传输系统发送模块,重点阐述了16:12转换器芯片的设计.首先基于高速收发器设计高速接口:在接收端采用2种方法实现SFI-5接口的17路数据相位对齐; 在发送端由片外时钟驱动发送锁相环,同时增加同步措施,以满足高速收发器时钟管理单元对跨时钟域数据传输的要求,保证收发器的稳定工作.在此基础上,设计出便于后续测试的转换芯片时钟网络.同时设计出基于SDH的帧同步电路、去斜移电路和16:12映射模块,实现数据从SFI-5接口向VSR-5接口的转换; 其中去斜移电路能够动态地去除512 bits的斜移量.在Signaltap Ⅱ下的测试结果验证了时序的正确性,误码率也符合小于10-12的设计指标.
Abstract:
Stratix Ⅱ GX FPGA from the Altera Corporation is employed to implement the transmitter module in a 40 Gbit/s very short reach optical transmission system. This paper focuses on the design of 16:12 converter. The high speed interface is designed based on the high speed transceiver: At the receiver, two methods are adopted to align the phase of the 17-channel data; at the transmitter, additional synchronization measure is taken to satisfy the demand from the clock management unit(CMU)to the data transmission between asynchronous clock domains, ensuring the stability of the transceiver. On these bases, the clock network is implemented by considering the reliability and the facility of the follow-up testing. Meantime, a frame aligner based on a synchronous digital hierarchy(SDH)structure, as well as the deskew circuit and the 16:12 mapping module is devised, achieving the conversion of data from SFI-5 interface to VSR-5 interface; the deskew module can eliminate the skew of 512 bits dynamically. The testing results using Signaltap Ⅱ verify the validity of the design. Measured by the Agilent 81250, the error bit rates also meet the design index of being less than 10-12.

参考文献/References:

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相似文献/References:

[1]王晓明,王志功,黄頲,等.甚短距离光传输技术[J].东南大学学报(自然科学版),2003,33(3):257.[doi:10.3969/j.issn.1001-0505.2003.03.003]
 Wang Xiaoming,Wang Zhigong,Huang Ting,et al.Very short reach optical transmission technology[J].Journal of Southeast University (Natural Science Edition),2003,33(4):257.[doi:10.3969/j.issn.1001-0505.2003.03.003]

备注/Memo

备注/Memo:
作者简介: 徐捷(1983—),男,硕士生; 胡庆生(联系人),女,博士,教授,博士生导师,qshu@seu.edu.cn.
基金项目: 国家高技术研究发展计划(863计划)资助项目(2006AA01Z239).
引文格式: 徐捷,胡庆生,许多,等.40 Gbit/s甚短距离光传输系统发送模块的设计与实现[J].东南大学学报:自然科学版,2009,39(4):656-661.[doi:10.3969/j.issn.1001-0505.2009.04.002]
更新日期/Last Update: 2009-07-20