[1]苏燕,冯军,施欢东.0.8V低功耗高速1:2分频器[J].东南大学学报(自然科学版),2010,40(6):1152-1156.[doi:10.3969/j.issn.1001-0505.2010.06.005]
 Su Yan,Feng Jun,Shi Huandong.0.8V low power high-speed 1:2 frequency divider[J].Journal of Southeast University (Natural Science Edition),2010,40(6):1152-1156.[doi:10.3969/j.issn.1001-0505.2010.06.005]
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0.8V低功耗高速1:2分频器()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
40
期数:
2010年第6期
页码:
1152-1156
栏目:
电路与系统
出版日期:
2010-11-20

文章信息/Info

Title:
0.8V low power high-speed 1:2 frequency divider
作者:
苏燕 冯军 施欢东
东南大学射频与光电集成电路研究所,南京 210096
Author(s):
Su Yan Feng Jun Shi Huandong
Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China
关键词:
分频器 单端动态负载锁存器 低电压
Keywords:
frequency divider single-end dynamic loading latch low voltage
分类号:
TN402
DOI:
10.3969/j.issn.1001-0505.2010.06.005
摘要:
采用UMC 0.13μm CMOS标准工艺,设计并实现了一种最高工作频率为17GHz的1:2分频器芯片.该芯片由基本分频器单元和输入输出缓冲组成.设计中为使分频器在低电源电压下正常工作,通过分析不同高速锁存器的结构特点,选择单端动态负载锁存器作为基本分频器单元.对单端动态负载锁存器进行直流分析可知,降低电源电压对采样模式的影响比保持模式大.在片测试结果表明:芯片电源电压最低可达0.8V; 当电源电压为0.8V时,芯片在3~17GHz频率范围内正常工作; 当输入信号频率分别为3和17GHz时,在10MHz频偏处,输出信号的相位噪声分别为-124.44和-120.62dBc/Hz.芯片面积为412μm×338μm,总功耗为3.84mW.
Abstract:
By using the United Microelectronics Corporation(UMC)0.13μm standard complementary metal oxide semiconductor(CMOS)process, a 1:2 frequency divider, which can work on the maximum operation frequency up to 17GHz, is designed. The circuits are composed of a frequency divider cell and input/output(I/O)buffers. To design a frequency divider working under a low supply voltage, the structure characteristics of different high speed latches are analyzed and a single-end dynamic loading latch is employed as the basic cell. The direct current(DC)analysis is carried out on the single-end dynamic loading latch. Lowering the supply voltage exhibits a more obvious effect on the sensing mode than on the latching mode. The test results show that the lowest supply voltage on which the divider can work is 0.8V. The frequency range is 3 to 17GHz with a 0.8V supply voltage. When the input signal frequencies are 3 and 17GHz, the measured phase noises are -124.44 and -120.62dBc/Hz at 10MHz offset from the center frequency, respectively. The circuit occupies 412μm×338μm and the total power consumption is only 3.84mW.

参考文献/References:

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备注/Memo

备注/Memo:
作者简介: 苏燕(1986—),女,硕士生; 冯军(联系人),女,博士,教授,博士生导师,fengjun-seu@seu.edu.cn.
引文格式: 苏燕,冯军,施欢东.0.8V低功耗高速1:2分频器[J].东南大学学报:自然科学版,2010,40(6):1152-1156. [doi:10.3969/j.issn.1001-0505.2010.06.005]
更新日期/Last Update: 2010-11-20