[1]柏娜,冯越,尤肖虎,等.极低电源电压和极低功耗的亚阈值SRAM存储单元设计[J].东南大学学报(自然科学版),2013,43(2):268-273.[doi:10.3969/j.issn.1001-0505.2013.02.008]
 Bai Na,Feng Yue,You Xiaohu,et al.An ultra-low-supply-voltage ultra-low-power subthreshold SRAM bitcell design[J].Journal of Southeast University (Natural Science Edition),2013,43(2):268-273.[doi:10.3969/j.issn.1001-0505.2013.02.008]
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极低电源电压和极低功耗的亚阈值SRAM存储单元设计()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
43
期数:
2013年第2期
页码:
268-273
栏目:
电路与系统
出版日期:
2013-03-20

文章信息/Info

Title:
An ultra-low-supply-voltage ultra-low-power subthreshold SRAM bitcell design
作者:
柏娜123冯越2尤肖虎3时龙兴1
1东南大学国家专用集成电路系统工程技术研究中心, 南京 210096; 2安徽大学电子信息工程学院, 合肥 230601; 3东南大学移动通信国家重点实验室, 南京 210096
Author(s):
Bai Na123 Feng Yue2 You Xiaohu3 Shi Longxing1
1National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
2School of Electronics and Information Engineering, Anhui University, Hefei 230601, China
3National Mobile Communications Research Laboratory, Southeast University, Nanjing 210096, China
关键词:
极低功耗 亚阈值 SRAM存储单元 泄漏电流
Keywords:
ultra-low power subthreshold SRAM bitcell leakage current
分类号:
TN402;TP333
DOI:
10.3969/j.issn.1001-0505.2013.02.008
摘要:
提出一款可以工作在极低电源电压条件下,功耗极低的亚阈值SRAM存储单元.为使本设计在极低电源电压(200 mV)条件下依然能够保持足够的鲁棒性,采用差分读出方式和可配置的操作模式.为极大限度地降低电路功耗,采用自适应泄漏电流切断机制,该机制在不提高动态功耗与不增加性能损失的前提下,可同时降低动态操作(读/写操作)和静态操作时的泄漏电流.基于IBM 130 nm工艺,实现了一款256×32 bit大小的存储阵列.测试结果表明,该存储阵列可以在200 mV电源电压条件下正常工作,功耗(包括动态功耗和静态功耗)仅0.13 μW,为常规六管存储单元功耗的1.16%.
Abstract:
An ultra-low-supply-voltage ultra-low-power subthreshold static random access memory(SRAM)bitcell with a self-adaptive leakage current cutoff scheme is proposed for ultra-low-supply-voltage(200 mV)applications. To achieve enough robustness in those supply voltage, the differential sensing method and the reconfigurable operating mode are adopted. With self-adaptive leakage current cutoff scheme, the proposed design can reduce the leakage current of dynamic and static operation without increasing the dynamic energy consumption and the performance loss. A 256×32 bit SRAM array is fabricated based on IBM 130 nm CMOS technology. And testing results demonstrate that the total power(dynamic power and standby power)consumption of SRAM at 200 mV is 0.13 μW which is only 1.16% of conventional 6T SRAM.

参考文献/References:

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备注/Memo

备注/Memo:
作者简介: 柏娜(1977—),女,博士,副教授; 时龙兴(联系人),男,博士,教授,博士生导师,lxshi@seu.edu.cn.
基金项目: 国家自然科学基金资助项目(61204039)、人力资源和社会保障部留学回国人员科研启动基金资助项目、国家核高基重大专项资助项目(2011ZX01034-001-002-003)、东南大学博士后重点科研资助计划资助项目.
引文格式: 柏娜,冯越,龙肖虎,等.极低电源电压和极低功耗的亚阈值SRAM存储单元设计[J].东南大学学报:自然科学版,2013,43(2):268-273. [doi:10.3969/j.issn.1001-0505.2013.02.008]
更新日期/Last Update: 2013-03-20