[1]谢世健,赵文霞.高速CMOS电路合理结构的设计[J].东南大学学报(自然科学版),1984,14(2):106-113.[doi:10.3969/j.issn.1001-0505.1984.02.012]
 Xie Shi-jian. Zhao Wen-xia.Design of Reasonable Structure for High Speed CMOS Circuits[J].Journal of Southeast University (Natural Science Edition),1984,14(2):106-113.[doi:10.3969/j.issn.1001-0505.1984.02.012]
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高速CMOS电路合理结构的设计()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
14
期数:
1984年第2期
页码:
106-113
栏目:
本刊信息
出版日期:
1984-06-20

文章信息/Info

Title:
Design of Reasonable Structure for High Speed CMOS Circuits
作者:
谢世健赵文霞
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Author(s):
Xie Shi-jian. Zhao Wen-xia
关键词:
倒相器 宽长比 单元电路 沟道宽度 传输延迟时间 或非门 与非门 设计方法 几何结构 下降时间
分类号:
+
DOI:
10.3969/j.issn.1001-0505.1984.02.012
摘要:
本文仔细地分析了铝栅和条状硅栅CM。S结构的节点电容与几何结构、物理、材料和工艺参数关系;推出了较为精确的节点电容表达式;提出CMOS倒相器、与非门、或非门等基本单元电路设计合理结构的理论,为决定申,小规模高速CMOS电路各级门电路经济合理的几何结构提供了一种有价值的设计方法,是提高CMOS电路速度一种有效途径。本设计理论已应用于六倒相器,计数器等多种条状栅CMOs电路的设计,并获得令人满意的交流参数。
Abstract:
This paper analyses the relationship between node Capacitance of Al-gate and Si-gate CMOS structure and geometric layout, material characteristics, physical and technological parameters in details; derives the expressions of node capacitance with higher accuracy. The theory to establish reasonable structure for circuit design of CMOS inverter NAND gate and NOR gate, etc, has been developed and a valuable design method for economically and reasonably determ ining geometric structure of each gate for small and middle scale high speed CMOS circuit has been provided. This design ,nethod is an efficient way to increase the speed of COMS circuit. By applying this design theory to Hexinverters and counters, etc. CMOS circuits, the excellent A. C. parameters have been obtained.

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[2]谢世健,丁璇英.封闭硅栅CMOS电路经济结构设计[J].东南大学学报(自然科学版),1984,14(4):76.[doi:10.3969/j.issn.1001-0505.1984.04.008]
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更新日期/Last Update: 2013-05-01