[1]程树东,郁炜嘉,朱恩,等.基于PHEMT工艺的5 GHz锁相环芯片[J].东南大学学报(自然科学版),2004,34(2):157-160.[doi:10.3969/j.issn.1001-0505.2004.02.004]
 Cheng Shudong,Yu Weijia,Zhu En,et al.5 GHz PLL chip using PHEMT technology[J].Journal of Southeast University (Natural Science Edition),2004,34(2):157-160.[doi:10.3969/j.issn.1001-0505.2004.02.004]
点击复制

基于PHEMT工艺的5 GHz锁相环芯片()
分享到:

《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
34
期数:
2004年第2期
页码:
157-160
栏目:
信息与通信工程
出版日期:
2004-03-20

文章信息/Info

Title:
5 GHz PLL chip using PHEMT technology
作者:
程树东 郁炜嘉 朱恩 王雪艳 沈祯 王志功
东南大学射频与光电集成电路研究所, 南京 210096
Author(s):
Cheng Shudong Yu Weijia Zhu En Wang Xueyan Shen Zhen Wang Zhigong
Institute of RF & OE-ICs, Southeast University, Nanjing 210096, China
关键词:
锁相环 鉴相器 压控振荡器 砷化镓赝晶高电子迁移率器件工艺
Keywords:
PLL phase detector VCO GaAs PHEMT-technology
分类号:
TN911.8
DOI:
10.3969/j.issn.1001-0505.2004.02.004
摘要:
给出了基于0.2 μm砷化镓赝晶高电子迁移率器件工艺设计的高速锁相环芯片的电路结构、性能分析与测试结果.芯片采用吉尔伯特结构的鉴相器和交叉耦合负阻差分环形压控振荡器,总面积为1.15 mm×0.75 mm.锁定时中心工作频率为4.44 GHz,锁定范围约为360 MHz,在100 kHz频偏处的单边带相位噪声约-107 dBc/Hz,经适当修改后可应用于光纤通信系统中的时钟数据恢复电路.
Abstract:
A 5 GHz phase-locked loop(PLL)chip based on 0. 2 μm GaAs PHEMT(pseudomorphic high-electron-mobility transistor)technology has been realized and characterized. The chip size is 1. 15 mm×0. 75 mm with a phase detector using Gilbert cell and a differential ring voltage controlled oscillator(VCO)using cross-coupled negative resistance. The locking range is approximately 360 MHz with a center frequency of 4. 44 GHz and the phase noise is -107 dBc/Hz at 100 kHz offset. The PLL chip can be adopted in the clock and data recovery circuits of the optic-fiber communication systems after appropriate modification.

参考文献/References:

[1] 刘丽,王志功,顾峥.基于0.25 μm CMOS工艺的2.5GHz 锁相环电路[A].见:2001全国光电子器件与集成技术会议论文集[C].桂林,2001.70-72.
  Liu Li,Wang Zhigong,Gu Zheng.2.5 GHz PLL using 0.25 μm CMOS Technology [A].In:Photoelectron Device and Integrated Technology Symposium of China 2001 [C].Guilin,2001.70-72.
[2] 顾峥.光纤通信中的超高速单片时钟恢复电路[D].南京:东南大学无线电工程系,2001.
[3] Razavi Behzad.Monolithic phase-locked loops and clock recovery circuits theory and design[M].New York:IEEE Press,1996.1-39.
[4] Razavi Behzad.Design of analog CMOS integrated circuits [M].Singapore:McGraw-Hill,2001.482-576.
[5] 王志功.光纤通信集成电路设计[M].北京:高等教育出版社,2003.239-248.
[6] Thiede Andreas,Wang Zhigong,Schlechtweg Michael,et al.Mixed signal integrated circuits based on GaAs HEMTs [J].IEEE Trans on VLSI Systems, 1998,6(1):6-17.
[7] 刘军,王志功,谢婷婷,等.共面波导(CPW)在单片电路设计中的应用研究[A].见:1999 全国微波毫米波会议论文集 [C].长沙,1999.315-317.
  Liu Jun,Wang Zhigong,Xie Tingting,et al.The applied research of CPW(go-planar waveguide)on monolithic circuit design [A].In: Microwave and Millimeter Symposium of China 1999 [C].Changsha,1999.315-317.
[8] Razavi Behzad,Lee Kwing F,Yan Ran H.Design of high-speed,low-power frequency dividers and phase-locked loops in deep submicron CMOS [J].IEEE Journal of Solid-State Circuits,1995,30(2):101-109.

相似文献/References:

[1]王晓俊,周杏鹏,徐凯,等.基于改进相差法的超声波微流量检测[J].东南大学学报(自然科学版),2011,41(6):1202.[doi:10.3969/j.issn.1001-0505.2011.06.015]
 Wang Xiaojun,Zhou Xingpeng,Xu Kai,et al.Ultrasonic micro-flow measurement based on improved phase-difference method[J].Journal of Southeast University (Natural Science Edition),2011,41(2):1202.[doi:10.3969/j.issn.1001-0505.2011.06.015]
[2]衣承斌,张朋,陈天授.低频宽带锁相倍频器的研究[J].东南大学学报(自然科学版),1983,13(3):108.[doi:10.3969/j.issn.1001-0505.1983.03.013]
 Yi Cheng-bin,Zhang Peng,and Chen Tian-shou.A Study of the Phase-Locked Frequency Multiplier for Low Frequency Wide Band Applications[J].Journal of Southeast University (Natural Science Edition),1983,13(2):108.[doi:10.3969/j.issn.1001-0505.1983.03.013]
[3]宫兆祥,周寿根.1.7GHZ取样锁相固态源[J].东南大学学报(自然科学版),1979,9(4):98.[doi:10.3969/j.issn.1001-0505.1979.04.009]
 Gong Zhao-xiang,Zhou Shou-gen.1.7 GHZ Phase-Locking Solid-State Oscillator[J].Journal of Southeast University (Natural Science Edition),1979,9(2):98.[doi:10.3969/j.issn.1001-0505.1979.04.009]
[4]蔡志匡,徐亮,任力争,等.基于MRV原理的锁相环抖动BIST电路优化与实现[J].东南大学学报(自然科学版),2014,44(3):482.[doi:10.3969/j.issn.1001-0505.2014.03.006]
 Cai Zhikuang,Xu Liang,Ren Lizheng,et al.Optimization and implementation of PLL jitter BIST circuit based on MRV technique[J].Journal of Southeast University (Natural Science Edition),2014,44(2):482.[doi:10.3969/j.issn.1001-0505.2014.03.006]

备注/Memo

备注/Memo:
基金项目: 国家863 计划资助项目(2001AA312060).
作者简介: 程树东(1973—),男,硕士生; 朱恩(联系人),男,博士, 教授, 博士生导师,zhuenpro@seu.edu.cn.
更新日期/Last Update: 2004-03-20