[1]张惠国,陈珍海,孙伟锋,等.双通道可重构14 bit 125 MS/s流水线ADC[J].东南大学学报(自然科学版),2017,47(4):649-654.[doi:10.3969/j.issn.1001-0505.2017.04.004]
 Zhang Huiguo,Chen Zhenhai,Sun Weifeng,et al.Dual-channel reconfigurable 14 bit 125 MS/s pipelined ADC[J].Journal of Southeast University (Natural Science Edition),2017,47(4):649-654.[doi:10.3969/j.issn.1001-0505.2017.04.004]
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双通道可重构14 bit 125 MS/s流水线ADC()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
47
期数:
2017年第4期
页码:
649-654
栏目:
电路与系统
出版日期:
2017-07-20

文章信息/Info

Title:
Dual-channel reconfigurable 14 bit 125 MS/s pipelined ADC
作者:
张惠国12陈珍海13孙伟锋1周德金3于宗光3魏敬和3
1东南大学国家ASIC工程技术研究中心, 南京210004; 2常熟理工学院物理与电子工程学院, 常熟215500; 3中国电子科技集团第五十八研究所, 无锡214035
Author(s):
Zhang Huiguo12 Chen Zhenhai13 Sun Weifeng1 Zhou Dejin3 Yu Zongguang3 Wei Jinghe3
1National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210004, China
2School of Physics and Electronic Engineering, Changshu Institute of Technology, Changshu 215500, China
3 No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
关键词:
流水线模数转换器 可重构 时间交织 电流模发送器
Keywords:
pipelined analog-to-digital converter reconfigurable time-interleaved current mode transmitter
分类号:
TN453
DOI:
10.3969/j.issn.1001-0505.2017.04.004
摘要:
提出了一种双通道可重构14 bit 125 MS/s流水线模数转换器(ADC).该双通道14 bit ADC可工作在并行双通道14 bit 125 MS/s、时间交织14 bit 250 MS/s以及求和15 bit 125 MS/s三种模式.为抑制通道间失配误差的影响,提出一种数模混合前台校准技术.为减少ADC输出端口数目,数据输出由高速串行数据发送器驱动,并且其工作模式有1.75, 2, 3.5 Gbit/s三种.该ADC电路采用0.18 μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,对于相同的10.1 MHz的输入信号,该ADC电路在14 bit 125 MS/s模式下的SNR和SFDR分别为72.5 dBFS和83.1 dB,在14 bit 250 MS/s模式下的SNR和SFDR分别为71.3 dBFS和77.6 dB,在15 bit 125 MS/s模式下的SNR和SFDR分别为75.3 dBFS和87.4 dB.芯片总体功耗为461 mW,单通道ADC内核功耗为210 mW,面积为1.3×4 mm2.
Abstract:
A dual-channel reconfigurable 14 bit 125 MS/s pipelined ADC(analog to digital converter)is presented.The dual channel 14 bit ADC can work in parallel dual 14 bit 125 MS/s mode, time interleaved 14 bit 250 MS/s mode, and sum 15 bit 125 MS/s mode. To reject the influence of the channel mismatch error, a mix-signal for-ground calibration technique is proposed. To reduce the digital output pins, the high speed serial transmitter is introduced to drive the digital output code, which can work in 1.75, 2 and 3.5 Gbit/s modes. The ADC is fabricated with 0.18 μm 1.8 V 1P5M CMOS(complementary metal oxide semiconductor)technology.Test results show that the ADC achieves the signal to noise ratio(SNR)of 72.5 dBFS and spurious free dynamic range(SFDR)of 83.1 dB for parallel dual 14 bit 125 MS/s mode, the SNR of 71.3 dBFS and SFDR of 77.6 dB for time interleaved 14 bit 250 MS/s mode, the SNR of 75.3 dBFS and SFDR of 87.4 dB for sum 15 bit 125 MS/s mode, with 10.1 MHz input at full sampling speed. The ADC consumes the total power of 461 mW, while the single 14 bit ADC core consumes the power of 210 mW and occupies an area of 1.3×4 mm2.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2016-11-15.
作者简介: 张惠国(1978—),男,博士,副教授;孙伟锋(联系人),男,博士,教授,博士生导师, swffrog@seu.edu.cn.
基金项目: 国家自然科学基金资助项目(61474092)、安徽高校自然科学研究重点资助项目(KJ2017A396)、教育部留学回国人员科研启动基金资助项目.
引用本文: 张惠国,陈珍海,孙伟锋,等.双通道可重构14 bit 125 MS/s流水线ADC[J].东南大学学报(自然科学版),2017,47(4):649-654. DOI:10.3969/j.issn.1001-0505.2017.04.004.
更新日期/Last Update: 2017-07-20