[1]易茂祥,吴清焐,袁诗琪,等.针对抗老化门替换技术的关键门识别算法[J].东南大学学报(自然科学版),2018,48(3):411-416.[doi:10.3969/j.issn.1001-0505.2018.03.006]
 Yi Maoxiang,Wu Qingwu,Yuan Shiqi,et al.Critical gate identification algorithm for anti-aging gate replacement technology[J].Journal of Southeast University (Natural Science Edition),2018,48(3):411-416.[doi:10.3969/j.issn.1001-0505.2018.03.006]
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针对抗老化门替换技术的关键门识别算法()
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《东南大学学报(自然科学版)》[ISSN:1001-0505/CN:32-1178/N]

卷:
48
期数:
2018年第3期
页码:
411-416
栏目:
电路与系统
出版日期:
2018-05-20

文章信息/Info

Title:
Critical gate identification algorithm for anti-aging gate replacement technology
作者:
易茂祥吴清焐袁诗琪张姚丁力梁华国
合肥工业大学电子科学与应用物理学院, 合肥 230009
Author(s):
Yi Maoxiang Wu Qingwu Yuan Shiqi Zhang Yao Ding Li Liang Huaguo
School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, China
关键词:
负偏置温度不稳定性 门替换技术 时序分析 电路老化 关键门
Keywords:
NBTI(negative bias temperature instability) gate replacement technology timing analysis circuit aging critical gate
分类号:
TN407
DOI:
10.3969/j.issn.1001-0505.2018.03.006
摘要:
为解决现有门替换技术应用中存在的时延仿真不精确和关键门选取冗余问题,对时序分析方法进行改进,通过引入电路内部节点信息,准确预测电路NBTI老化.然后,提出了一种门替换技术应用下的关键门识别算法,定义了表征门电路抗NBTI老化能力的度量公式,将其作为电路老化关键门的识别依据,用于提高关键门识别精度和效率.基于45 nm PTM工艺库和ISCAS85基准电路的仿真结果表明,应用改进门替换技术进行电路抗NBTI老化设计得到的电路时延退化改善率平均值为25.11%,较现有方案提高13.24%,而反映硬件开销的平均门替换率仅为5.82%,明显低于现有方案的11.95%.因此,所提方案仅以较低的硬件开销便可获得较好的门替换技术抗老化效果.
Abstract:
To solve the problems of inaccurate delay simulation and redundant critical gate selection in the application of the existing gate replacement technology, a circuit timing analysis method is improved to accurately predict the NBTI(negative bias temperature instability)aging of circuits by introducing the information of the internal nodes. Then, a critical gate identification algorithm for the application of the gate replacement technology is proposed. A measure formula for characterizing the anti-NBTI aging ability of gate circuits is defined and served as a basis for identifying the circuit critical gate to improve the accuracy and the efficiency of critical gate identification. The simulation results based on 45 nm PTM(predictive transistor model)and ISCAS85 benchmark circuits show that the improvement rate of circuit delay degradation using the improved anti-NBTI aging scheme is 25.11%, which is 13.24% higher than that of the existing one. However, the average gate replacement rate representing the hardware cost is only 5.82%, which is significantly lower than that of the existing schemes(11.95%). The proposed scheme can obtain good anti-aging effect of the gate replacement technology with low hardware overhead.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2017-11-08.
作者简介: 易茂祥(1964—),男,博士,教授,mxyi126@126.com.
基金项目: 国家自然科学基金资助项目(61371025,61574052,61674048).
引用本文: 易茂祥,吴清焐,袁诗琪,等.针对抗老化门替换技术的关键门识别算法[J].东南大学学报(自然科学版),2018,48(3):411-416. DOI:10.3969/j.issn.1001-0505.2018.03.006.
更新日期/Last Update: 2018-05-20